SH7205 Datasheet, PDF (712/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 13 Compare Match Timer (CMT)
13.5 Usage Notes
13.5.1 Conflict between Write and Compare-Match Processes of CMCNT
When the compare match signal is generated in the T2 cycle while writing to CMCNT, clearing
CMCNT has priority over writing to it. In this case, CMCNT is not written to. Figure 13.5 shows
the timing to clear the CMCNT counter.
Peripheral clock
(Pφ)
Address signal
Internal write signal
Counter clear signal
CMCSR write cycle
T1
T2
CMCNT
CMCNT
N
H'0000
Figure 13.5 Conflict between Write and Compare Match Processes of CMCNT
Rev. 1.00 Mar. 25, 2008 Page 680 of 1868
REJ09B0372-0100