SH7205 Datasheet, PDF (1132/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
Initial
Bit
Bit Name Value R/W Description
0
4ECCEXST 0
R/(W)* 4-Symbol ECC Correction Execution
When an ECC error is detected, this bit is set and error
counting or generation of correction pattern is executed.
Generation of correction pattern is executed for a sector.
0: Error counting and correction pattern generation is
stopped.
1: Error counting or correction pattern generation is
executed.
If the 4ECCCORRECT bit in FLCMNCR is set to 1,
reading is stopped while 4ECCEXST is set to 1 and
reading is restarted when 4ECCEXST is cleared. Do not
write 0 to this bit until 4ECCEND bit is set to 1.
23.3.16 4-Symbol ECC Error Count Register (FL4ECCCNT)
FL4ECCCNT is a 32-bit readable register that indicates the number of errors detected by the 4-
symbol ECC circuit. Only 0 can be written to this register. To clear this register, write 0 to all bits.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
ERRCNT[10:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
ERRMAX[2:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
31 to 27 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1100 of 1868
REJ09B0372-0100