SH7205 Datasheet, PDF (1022/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 20 Controller Area Network (RCAN-TL1)
Bit5 to 0 — RCAN-TL1 Timer Prescaler (TPSC[5:0]): This control field allows the timer
source clock (4*[RCAN-TL1 system clock]) to be divided before it is used for the timer. This
function is available only in event-trigger mode. In time trigger mode (CMAX is not 3'b111), one
nominal Bit Timing (= one bit length of CAN bus) is automatically chosen as source clock of
TCNTR.
The following relationship exists between source clock period and the timer period.
Bit[5:0]: TPSC[5:0]
000000
000001
000010
000011
000100
......
......
111111
Description
1 X Source Clock (initial value)
2 X Source Clock
3 X Source Clock
4 X Source Clock
5 X Source Clock
......
......
64 X Source Clock
(2) Cycle Maximum/Tx-Enable Window Register (CMAX_TEW)
This register is a 16-bit read/write register. CMAX specifies the maximum value for the cycle
counter (CCR) for TT Transmissions to set the number of basic cycles in the matrix system. When
the Cycle Counter reaches the maximum value (CCR = CMAX), after a full basic cycle, it is
cleared to zero and an interrupt is generated on IRR.10.
TEW specifies the width of Tx-Enable window.
• CMAX_TEW (Address = H'084)
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
CMAX[2:0]
-
-
-
-
TEW[3:0]
Initial value: 0
0
0
0
0
1
1
1
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R R/W R/W R/W R
R
R
R R/W R/W R/W R/W
Bits 15 to 11: Reserved. The written value should always be ‘0’ and the returned value is ‘0’.
Rev. 1.00 Mar. 25, 2008 Page 990 of 1868
REJ09B0372-0100