SH7205 Datasheet, PDF (216/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
7.3.13 IRQ Interrupt Enable Control Registers (C0IRQER, C1IRQER)
C0IRQER and C1IRQER are 16-bit registers that control whether to enable or disable acceptance
of IRQ interrupt requests by processors CPU0 and CPU1. If the same bits in both registers
C0IRQER and C1IRQER are set to 0, the acceptance by CPU0 is enabled.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
IRQ7 IRQ6 IRQ5 IRQ4 IRQ3 IRQ2 IRQ1 IRQ0
Initial value: *
*
*
*
*
*
*
*
*
*
*
*
*
*
*
*
R/W: R
R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W
Initial
Bit
Bit Name Value R/W Description
15 to 8 
*
R
Reserved
In C0IRQER, these bits are always read as 1. The write
value should always be 1.
In C1IRQER, these bits are always read as 0. The write
value should always be 0.
7
IRQ7
*
R/W IRQn Interrupt Enable
6
IRQ6
*
R/W These bits select whether to enable IRQn interrupt request
5
IRQ5
*
R/W ^inputs.
4
IRQ4
*
R/W ^{0: IRQn interrupt request input is disabled.}
1: IRQn interrupt request input is enabled.
3
IRQ3
*
R/W
2
IRQ2
*
R/W
1
IRQ1
*
R/W
0
IRQ0
*
R/W
[Legend]
n = 7 to 0
Note: * The initial value is 1 for C0IRQER and 0 for C1IRQER.
Rev. 1.00 Mar. 25, 2008 Page 184 of 1868
REJ09B0372-0100