SH7205 Datasheet, PDF (310/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
Initial
Bit
Bit Name Value R/W Description
29, 28 PBCNT[1:0] 00
R/W Page Access Bit Boundary Select
These bits select the bit boundary for page access
operation. When the bit boundary specified by PBCNT is
exceeded during page access, page access operation is
halted temporarily (the CSn signal is negated), and then
page access operation begins again. The value written to
these bits is valid only when either of the PWENB bit or
the PRENB bit is set to 1.
00: 64-bit boundary
01: 128-bit boundary
10: 256-bit boundary
11: Setting prohibited
27, 26 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
25
PWENB 0
R/W Page Write Access Enable
This bit is used to enable page write access.
0: Page write access disabled
1: Page write access enabled
24
PRENB
0
R/W Page Read Access Enable
This bit is used to enable page read access.
0: Page read access disabled
1: Page read access enabled
23 to 20 
All 0 R
Reserved
These bits are always read as 0. The write value should
always be 0.
19
EWENB 0
R/W External Wait Enable
This bit is used to enable or disable external wait input.
When EWENB is set to 1, external wait input is enabled
and the number of wait states per cycle can be controlled
using the external wait signal (WAIT). In this case wait
cycles are inserted while the WAIT signal is on a low level.
When EWENB is cleared to 0, the WAIT signal is invalid.
0: External wait disabled
1: External wait enabled
Rev. 1.00 Mar. 25, 2008 Page 278 of 1868
REJ09B0372-0100