SH7205 Datasheet, PDF (544/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Bit
0
Note:
Initial
Bit Name Value R/W Description
OE3B
0
R/W Master Enable TIOC3B
This bit enables/disables the TIOC3B pin MTU2 output.
0: MTU2 output is disabled (inactive level)*
1: MTU2 output is enabled
* The inactive level is determined by the settings in timer output control registers 1 and 2
(TOCR1 and TOCR2). For details, refer to section 12.3.18, Timer Output Control
Register 1 (TOCR1), and section 12.3.19, Timer Output Control Register 2 (TOCR2).
Set these bits to 1 to enable MTU2 output in other than complementary PWM or reset-
synchronized PWM mode. When these bits are set to 0, low level is output.
12.3.18 Timer Output Control Register 1 (TOCR1)
TOCR1 is an 8-bit readable/writable register that enables/disables PWM synchronized toggle
output in complementary PWM mode/reset synchronized PWM mode, and controls output level
inversion of PWM output.
Bit: 7
6
5
- PSYE -
Initial value: 0
0
0
R/W: R R/W R
4
3
2
1
0
- TOCL TOCS OLSN OLSP
0
0
0
0
0
R R/(W)*³ R/W R/W R/W
Initial
Bit
Bit Name value R/W Description
7
—
0
R
Reserved
This bit is always read as 0. The write value should
always be 0.
6
PSYE
0
R/W PWM Synchronous Output Enable
This bit selects the enable/disable of toggle output
synchronized with the PWM period.
0: Toggle output is disabled
1: Toggle output is enabled
5, 4 —
All 0
R
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 512 of 1868
REJ09B0372-0100