SH7205 Datasheet, PDF (844/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
17.3.6 SS Control Register 2 (SSCR2)
SSCR2 is a register that selects the assert timing of the SCS pin, data output timing of the SSO
pin, and set timing of the TEND bit.
Bit: 7
6
5
4
3
2
1
0
-
-
- TENDSTS SCSATS SSODTS -
-
Initial value: 0
0
0
0
0
0
0
0
R/W: R
R
R R/W R/W R/W R
R
Initial
Bit
Bit Name Value R/W
7 to 5 
All 0
R
4
TENDSTS 0
R/W
3
SCSATS 0
R/W
2
SSODTS 0
R/W
1, 0 
All 0
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
Selects the timing of setting the TEND bit (valid in SSU
and master mode).
0: Sets the TEND bit when the last bit is being
transmitted
1: Sets the TEND bit after the last bit is transmitted
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0:
Min.
values
of
t
LEAD
and
t
LAG
are
1/2
×
t
SUcyc
1: Min. values of t_LEAD and t_LAG are 3/2 × t_SUcyc
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 812 of 1868
REJ09B0372-0100