SH7205 Datasheet, PDF (1389/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.10 Source E Read-In Area Setting Register for Output Block (MGR_SESET)
The register MGR_SESET sets the SE area. In a DMA transfer, the total number of pixels to be
transferred from the external memory space is obtained by SEWIDH × SEHIGH. The register
value is applied to the 2DG in synchronization with the VSYNC signal.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
SEHIGH
Initial value: -
-
-
-
-
-
-
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit: 15
-
Initial value: -
R/W: R
14 13
-
-
-
-
R
R
12 11 10
-
-
-
-
-
-
R
R
R
9
8
7
6
5
4
3
2
1
0
-
SEWIDH
-
0
0
0
0
0
0
0
0
0
R R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit name
31 to 25 
24 to 16 SEHIGH
15 to 9 
8 to 0 SEWIDH
Initial
Value
R/W
Undefined R
H'000
R/W
Undefined R
H'000
R/W
Description
Reserved
The read value is undefined. The write value should
always be 0.
SE Area Vertical Setting
These bits set the vertical height (number of lines) of
the rectangular area (SE area) to be transferred.
Valid range: 2 to 288 lines
Reserved
The read value is undefined. The write value should
always be 0.
SE Area Horizontal Setting
These bits set the horizontal width (number of pixels)
of the rectangular area (SE area) to be transferred.
Valid range: 2 to 511 pixels
• Only 16-bit access is enabled when the total number of pixels to be transferred (SEWIDH ×
SEHIGH) is odd; both 32-bit and 16-bit accesses are enabled when the value of (SEWIDH ×
SEHIGH) is even.
• The settings of this register should be the same as those of the MGR_MIXHS and
MGR_MIXVS registers.
SEWIDH bits = VLDPH bits in MGR_MIXHS
SEHIGH bits = VLDPV bits in MGR_MIXVS
Rev. 1.00 Mar. 25, 2008 Page 1357 of 1868
REJ09B0372-0100