SH7205 Datasheet, PDF (1103/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.2 Input/Output Pins
The pin configuration of the FLCTL is listed in table 23.1.
Table 23.1 Pin Configuration
Pin
Name
FCE
I/O
Output
Corresponding Flash
Memory Pin
NAND Type AND Type
CE
CE
NAF7 to I/O
NAF0
FCDE Output
I/O7 to I/O0
CLE
I/O7 to I/O0
CDE
FOE Output ALE
OE
FSC Output RE
SC
FWE Output WE
WE
FRB
Input
R/B
R/B
—*
—
WP
RES
—*
—
SE
—
Note: * Not supported in this LSI.
Function
Chip Enable
Enables flash memory connected to this LSI.
Data I/O
I/O pins for command, address, and data.
Command Latch Enable (CLE)
Asserted when a command is output.
Command Data Enable (CDE)
Asserted when a command is output.
Address Latch Enable (ALE)
Asserted when an address is output and negated when
data is input or output.
Output Enable (OE)
Asserted when data is input or when a status is read.
Read Enable (RE)
Reads data at the falling edge of RE.
Serial Clock (SC)
Inputs or outputs data synchronously with the SC.
Write Enable
Flash memory latches a command, address, and data at
the rising edge of WE.
Ready/Busy
Indicates ready state at high level; indicates busy state at
low level.
Write Protect/Reset
When this pin goes low, erroneous erasure or
programming at power on or off can be prevented.
Spare Area Enable
Used to access spare area. This pin must be fixed at low
in sector access mode.
Rev. 1.00 Mar. 25, 2008 Page 1071 of 1868
REJ09B0372-0100