SH7205 Datasheet, PDF (68/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Classification Symbol
Bus control
CS5 to CS0
RD
RD_WR/WE
WAIT
WE0/BC0/
DQM0
WE1/BC1/
DQM1
WE2/BC2/
DQM2
WE3/BC3/
DQM3
RAS
CAS
SDCS1,
SDCS0
SDWE
CKE
I/O Name
Function
O Chip select 5 to 0 Chip-select signals for external
memory or devices.
O Read
Indicates that data is read from an
external device.
O Read/write
Read/write signal.
I
Wait
Inserts wait cycles into bus cycles
during access to the external space.
O Byte select
Indicates a write access to bits 7 to 0
of data in external memory or device.
O Byte select
Indicates a write access to bits 15 to
8 of data in external memory or
device.
O Byte select
Indicates a write access to bits 23 to
16 of data in external memory or
device.
O Byte select
O RAS
O CAS
O Chip select
Indicates a write access to bits 31 to
24 of data in external memory or
device.
Connected to the RAS pin when
SDRAM is connected.
Connected to the CAS pin when
SDRAM is connected.
Connected to the CS pin when
SDRAM is connected.
O SDRAM write Connects to the WE pin of SDRAM if
enable
SDRAM is connected (SDWE).
O CK enable
Connected to the CKE pin when
SDRAM is connected.
Rev. 1.00 Mar. 25, 2008 Page 36 of 1868
REJ09B0372-0100