SH7205 Datasheet, PDF (1352/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 25 AT Attachment Packet Interface (ATAPI)
25.4.2 Initialization Procedure
(1) Setting the interface enable bit
Set the IFEN bit in ATAPI control 2 register to 1.
(2) Setting the timing register
Write an appropriate value to the following registers.
See the respective descriptions for what value is appropriate for each register.
• PIO timing register
• Multiword DMA timing register
• Ultra DMA timing register
25.4.3 PIO Transfer Mode Operation Procedure
Start
Master drive?
Yes
Write 1 to M/S bit
in ATAPI control register
No
Write 0 to M/S bit
in ATAPI control register
Write to or read
from task file register
End
Note: Never execute a PIO transfer while the ACT bit in the ATAPI status register is 1.
Figure 25.5 PIO Transfer Mode Operation Procedure
Rev. 1.00 Mar. 25, 2008 Page 1320 of 1868
REJ09B0372-0100