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SH7205 Datasheet, PDF (1013/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series | |||
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Section 20 Controller Area Network (RCAN-TL1)
Bit[15:1]:ABACK0 Description
0
[Clearing Condition] Writing â1â (Initial value)
1
Corresponding Mailbox has cancelled transmission of message (Data or
Remote Frame)
[Setting Condition]
Completion of transmission cancellation for corresponding mailbox
Bit 0 â This bit is always â0â as this is a receive-only mailbox. Writing a â1â to this bit position
has no effect and always read back as a â0â.
(5) Data Frame Receive Pending Register (RXPR1, RXPR0)
The RXPR1 and RXPR0 are 16-bit read/conditionally-write registers. The RXPR is a register that
contains the received Data Frames pending flags associated with the configured Receive
Mailboxes. When a CAN Data Frame is successfully stored in a receive mailbox the
corresponding bit is set in the RXPR. The bit may be cleared by writing a â1â to the corresponding
bit position. Writing a â0â has no effect. However, the bit may only be set if the mailbox is
configured by its MBC (Mailbox Configuration) to receive Data Frames. When a RXPR bit is set,
it also sets IRR1 (Data Frame Received Interrupt Flag) if its MBIMR (Mailbox Interrupt Mask
Register) is not set, and the interrupt signal is generated if IMR1 is not set. Please note that these
bits are only set by receiving Data Frames and not by receiving Remote frames.
⢠RXPR1
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
RXPR1[15:0]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W* R/W*
Note : * Only when writing a â1â to clear.
Bit 15 to 0 â Configurable receive mailbox locations corresponding to each mailbox position
from 31 to 16 respectively.
Bit[15:0]: RXPR1
0
1
Description
[Clearing Condition] Writing â1â (Initial value)
Corresponding Mailbox received a CAN Data Frame
[Setting Condition]
Completion of Data Frame receive on corresponding mailbox
Rev. 1.00 Mar. 25, 2008 Page 981 of 1868
REJ09B0372-0100
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