SH7205 Datasheet, PDF (1424/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(4) Input and Output Buffers
Since transfer to and from buffers SA, SB, DC, and SE in the 2DG must be handled by the DMAC
under CPU control, these buffers are mapped on memory spaces (SRAM spaces) of the CPU.
Table 26.7 shows the address map of the input and output buffers.
Table 26.7 Address Map of the Input and Output Buffers
Buffer Name
Abbreviation
Input buffer E for the output block (276 Kbytes) SE buffer
Input buffer A for the blitter (276 Kbytes)
SA buffer
Input buffer B for the blitter (276 Kbytes)
SB buffer
Output buffer C for the blitter (276 Kbytes)
DC buffer
Address
H'E8010000 to H'E8054FFC
H'E8060000 to H'E80A4FFC
H'E80B0000 to H'E80F4FFC
H'E8100000 to H'E8144FFC
Since the 2DG has fixed-size input and output buffers, an image processing is performed with
repeated DMA data transfer from these areas. Table 26.8 shows the specifications of the buffers.
Each buffer is configured as the double buffer structure.
Table 26.8 Specifications of Input and Output Buffers
Buffer Name
SE buffer
SA buffer
SB buffer
DC buffer
Size
16 bits × 512 words × two planes
16 bits × 64 words × two planes
16 bits × 64 words × two planes
16 bits × 256 words × two planes
Rev. 1.00 Mar. 25, 2008 Page 1392 of 1868
REJ09B0372-0100