SH7205 Datasheet, PDF (1124/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3.9 Ready Busy Timeout Setting Register (FLBSYTMR)
FLBSYTMR is a 32-bit readable/writable register that specifies the timeout time when the FRB
pin is busy.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
RBTMOUT[19:16]
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R R/W R/W R/W R/W
Bit: 15
Initial value: 0
R/W: R/W
14
0
R/W
13
0
R/W
12
0
R/W
11
0
R/W
10
0
R/W
9
8
7
6
RBTMOUT[15:0]
0
0
0
0
R/W R/W R/W R/W
5
0
R/W
4
0
R/W
3
0
R/W
2
0
R/W
1
0
R/W
0
0
R/W
Bit
Bit Name
31 to 20 —
Initial
Value R/W
All 0 R
19 to 0 RBTMOUT[19:0] H'00000 R/W
Description
Reserved
These bits are always read as 0. The write value
should always be 0.
Ready Busy Timeout
Specify timeout time (the number of Pφ clocks) in
busy state. When these bits are set to 0, timeout is
not generated.
Rev. 1.00 Mar. 25, 2008 Page 1092 of 1868
REJ09B0372-0100