SH7205 Datasheet, PDF (1273/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Bit
Bit Name
6
SQMON
5
PBUSY
4 to 2 
1, 0
PID[1:0]
Initial
Value
R/W
0
R
0
R
Undefined R
00
R/W
Description
Toggle Bit Confirmation
Indicates the expected value of the sequence toggle
bit for the next transaction of the pertinent pipe.
When the pertinent pipe is not for the isochronous
transfer, this bit toggles upon normal completion of
the transaction. However, this bit does not toggle
when a DATA-PID disagreement occurs during the
receiving transfer.
0: DATA0
1: DATA1
Pipe Busy
Indicates whether the pertinent pipe is currently used
for the USB bus.
This bit changes from 0 to 1 upon start of the USB
transaction for the pertinent pipe, and changes from
1 to 0 upon completion of one transaction.
Reading this bit after setting PID to NAK allows
confirming that modification of the pipe settings has
become possible.
0: The pertinent pipe is not currently used for the
USB bus.
1: The pertinent pipe is currently used for the USB
bus.
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Response PID
Specifies the response type for the next transaction
of the pertinent pipe.
The default setting of these bits is NAK. Modify the
setting to BUF to use the pertinent pipe for USB
transfer. Tables 24.15 and 18.16 show the basic
operation (operation when there are no errors in the
transmitted and received packets) of this module for
different PID bit settings.
Even if the PID bits are modified to NAK after this
module has issued S-Split of the split transaction for
the specified pipe (while CSSTS indicates 1), this
module continues the transaction until C-Split is
completed.
Rev. 1.00 Mar. 25, 2008 Page 1241 of 1868
REJ09B0372-0100