SH7205 Datasheet, PDF (1403/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
26.3.19 Resize Horizontal Starting Phase Register for Output Block (MGR_HPHAS)
The register MGR_HPHAS sets results of the starting position phase computation in the horizontal
direction for the output block resizing. The register value is applied to the output block in
synchronization with the VSYNC signal.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: -
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
MH1PHS_DCML
Initial value: -
-
-
-
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W
Bit
Bit name
31 to 12 
11 to 0 MH1PHS_
DCML
Initial
Value
R/W
Undefined R
H'000
R/W
Description
Reserved
The read value is undefined. The write value should
always be 0.
Horizontal Starting Position Phase Computation
Result Fractional Part
These bits set the fractional part of the starting-
position phase computation result in the horizontal
direction on the source side.
Rev. 1.00 Mar. 25, 2008 Page 1371 of 1868
REJ09B0372-0100