SH7205 Datasheet, PDF (1434/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
• In a DMA transfer to a buffer, if a continuous operand transfer is specified, the maximum
transfer size per operation should be set equal to the buffer size to be accessed (for example,
128 bytes for an SB buffer, and 960 bytes for an SE buffer).
If a continuous operand setting is selected, the transfer is continued until all transfer data that is
specified is transferred; therefore, the DMA transfer cannot be suspended on account of SB,
SA, DC, or SE buffer being full. For this reason, if a continuous operand transfer is to be
executed to the SB or SA buffer, line-by-line transfers should be performed solely on the basis
of one horizontal pixel setting = 32 or 64 pixels. In the case of a DC buffer, line-by-line
transfers should be performed solely on the basis of one horizontal pixel setting = 32, 64, 128,
or 256 pixels. In the case of an SE buffer, line-by-line transfers should be performed based on
the number of pixels that is set on the one horizontal pixel setting.
• If a single-operand transfer is specified in a DMA-based data transfer to a buffer, and if
another access equal to the buffer size is possible after completion of access equal to the buffer
size, the hardware automatically continues issuing DMA requests in order to align buffer
boundaries with operand boundaries. If another access equal to the buffer size is not possible,
the DMAC is held in standby until a condition that permits the issuance of a DMA request is
satisfied after the execution of internal processing.
• Examples of DMA transfer settings are given below:
The number of pixels transferred to the 2DG is set as horizontal width 64 pixels/3 vertical
lines, and each data item transferred consists of 1 pixel = 16 bits. In this case, the total number
of pixels transferred will be 16 bits × 64 pixels × 3 lines = 384 bytes. If such data is transferred
by a DMA transfer, the following two settings are possible:
Approach 1: If one data item = 16 bits/operand = eight data items/transfer mode = pipeline (or
cycle stealing)/transfer condition = single-operand transfer is set, and if the
number of bytes transferred per DMA transfer is 384 bytes, for each buffer
capacity the 2DG performs DMA request control to request a resumption of
DMA transfer each time the buffer becomes empty and performs DMA transfers.
Approach 2: If one data item = 16 bits/operand = eight data items/transfer mode = pipeline (or
cycle stealing)/transfer condition = continuous-operand transfer is set, and if the
number of bytes transferred per DMA transfer is 128 bytes and DMA is executed
three times by reloading, because the buffer becomes full in each DMA transfer,
for each buffer capacity the 2DG performs DMA request control to request a
resumption of DMA transfer each time the buffer becomes empty and performs
DMA transfers.
Rev. 1.00 Mar. 25, 2008 Page 1402 of 1868
REJ09B0372-0100