SH7205 Datasheet, PDF (1311/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Table 24.23 FIFO Port Function Settings
Register Name
C/DnFIFOSEL
Bit Name
RCNT
REW
DCLRM
C/DnFIFOCTR
DREQE
MBW
BIGEND
BVAL
BCLR
FRDY
DTLN
Function
Note
Selects DTLN read mode
Buffer memory rewind (re-read, rewrite)
Automatically clears data received for a For DnFIFO only
specified pipe after the data has been
read
Enable DMA transfer
For DnFIFO only
FIFO port access bit width
Selects endian for FIFO ports
Indicates writing to the buffer memory
has ended
Clears the buffer memory on the CPU
side
FIFO port ready monitor
Read to confirm the length of received
data
(a) FIFO Port Selection
Table 24.24 shows the pipes that can be selected with the various FIFO ports. The pipe to be
accessed is selected using the CURPIPE bit in C/DnFIFOSEL. After the pipe has been selected,
check to see whether the CURPIPE value for the last-written pipe has been read correctly (if the
previous pipe number is read, it indicates that the pipe changing processing is being done by this
module). When a correct value has been read from CURPIPE, confirm FRDY = 1 and then access
the FIFO port.
The bus width to be accessed should be selected using the MBW bit. The buffer memory access
direction is in accord with the ISEL bit setting for the DCP, and in accord with the DIR bit in
PIPEnCFG for other pipes.
Rev. 1.00 Mar. 25, 2008 Page 1279 of 1868
REJ09B0372-0100