SH7205 Datasheet, PDF (436/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
11.3.11 DMA Interrupt Control Register (DMICNT)
DMICNT controls DMA interrupt for each channel.
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN DIN
TM0 TM1 TM2 TM3 TM4 TM5 TM6 TM7 TM8 TM9 TM10 TM11 TM12 TM13
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R/W R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value R/W Description
31 to 18 DINTM0 H'0000 R/W DMA Interrupt Control
to
DINTM13
These bits are used to control whether to generate a DMA
transfer end interrupt of each channel to the interrupt controller.
Clearing these bits to 0 does not generate an interrupt request
to the interrupt controller. Setting these bits to 1 generates an
interrupt request to the interrupt controller when the DMA
transfer end condition is detected (for details, see section
11.5.2, DMA Interrupt Requests).
0: Interrupt disabled
1: Interrupt enabled
17 to 0 
All 0 R Reserved
These bits are always read as 0. The write value should always
be 0.
Note: Bits 31 to 18 correspond to channels 0 to 13.
Rev. 1.00 Mar. 25, 2008 Page 404 of 1868
REJ09B0372-0100