SH7205 Datasheet, PDF (308/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
10.4.3 SDRAMCm Control Register (SDCmCNT) (m = 0, 1)
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
-
-
-
-
BSIZE[1:0]
-
-
- EXENB
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R R/W R/W R
R
R R/W
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
-
Initial value: 0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
0
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit
Bit Name
31 to 22 
Initial
Value
All 0
21, 20 BSIZE[1:0] 00
19 to 17 
All 0
16
EXENB 0
15 to 0 
All 0
R/W Description
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W External Bus Width Select
These bits specify the width of the data bus for the
external device of the corresponding channel of SDRAMC.
10: 8-bit bus
00: 16-bit bus
01: 32-bit bus
R
Reserved
These bits are always read as 0. The write value should
always be 0.
R/W Operation Enable
This bit enables or disables the operation for the
corresponding channel of SDRAMC.
0: Operation disabled
1: Operation enabled
R
Reserved
These bits are always read as 0. The write value should
always be 0.
To disable the operation (EXENB = 0) for each channel, forcibly write out data tentatively stored
in internal write buffer. The procedure is as follows:
1. Execute read access to the channel whose operation is to be disabled.
2. Then, write 0 to the EXENB bit (operation disabled).
Rev. 1.00 Mar. 25, 2008 Page 276 of 1868
REJ09B0372-0100