SH7205 Datasheet, PDF (1211/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.18 SOF Output Configuration Register (SOFCFG)
SOFCFG specifies the transaction-enabled time and PIPEBRDY interrupt status clear timing.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
—
—
—
—
—
—
—
TRNEN
SEL
—
BRDYM
—
—
—
—
—
—
Initial value: -
-
-
-
-
-
-
0
-
0
-
-
-
-
-
-
R/W: R
R
R
R
R
R
R R/W R R/W R
R
R
R
R
R
Initial
Bit
Bit Name Value
R/W Description
15 to 9 
Undefined R
Reserved
Undefined values are read from these bits. The write
value should always be 0.
8
TRNENSEL 0
R/W Transaction-Enabled Time Select
Selects the transaction-enabled time either for full- or
low-speed communication, where is the time in which
this module issues tokens in a frame via the port.
0: For non-low-speed communication
1: For low-speed communication
Note: This bit is only valid when the host controller
function is selected. Even when the host
controller function is selected, the setting of
this bit has no effect on the transaction-
enabled time during high-speed
communication. This bit is used in common to
the two ports.
7

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
6
BRDYM
0
R/W PIPEBRDY Interrupt Status Clear Timing
Specifies the timing of clearing the BRDY interrupt
status for each pipe.
0: Clearing by writing 0
1: Automatic clearing by data reading from the FIFO
buffer or data writing to the FIFO buffer
5 to 0 
Undefined R
Reserved
Undefined values are read from these bits. The write
value should always be 0.
Note: Clear the value of the TRNENSEL bit to 0 when the function controller function is selected.
Rev. 1.00 Mar. 25, 2008 Page 1179 of 1868
REJ09B0372-0100