SH7205 Datasheet, PDF (469/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
• Cycle-stealing transfer mode
Single DMA transfer
Single operand transfer (read 1 wait)
Single operand transfer (read 1 wait)
Bus clock
DMA (S)
DMA (D)
DMAACK_N
DMATC_N (00)
DMATC_N (01)
DMATC_N (10)
DMATC_N (11)
DMA interrupt request
RD1
≥1
WR1
RD2
WR2
RD1
WR1
RD2
WR2
DTCM setting
• Pipelined transfer mode
Single DMA transfer
Single operand transfer (0 wait)
Last read of single Last write of single End of single
DMA transfer
DMA transfer DMA transfer
Single operand transfer (0 wait)
Bus clock
DMA (S)
DMA (D)
DMAACK_N
DMATC_N (00)
DMATC_N (01)
DMATC_N (10)
DMATC_N (11)
DMA interrupt request
RD1 RD2 RD3 RD4
WR1 WR2 WR3 WR4
≥1
RD1 RD2 RD3 RD4
WR1 WR2 WR3 WR4
DTCM setting
[Legend]
DMA (S): DMA source data transfer cycle on DMA read bus
DMA (D): DMA destination data transfer cycle on DMA write bus
Last read of single Last write of single End of single
DMA transfer
DMA transfer DMA transfer
Figure 11.6 Output Timing of DMA End Signal
Rev. 1.00 Mar. 25, 2008 Page 437 of 1868
REJ09B0372-0100