SH7205 Datasheet, PDF (556/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Initial
Bit
Bit Name value R/W Description
2 to 0 4VCOR[2:0] 000
R/W These bits specify the TCIV_4 interrupt skipping count
within the range from 0 to 7.*
For details, see table 12.39.
Note: * When 0 is specified for the interrupt skipping count, no interrupt skipping will be
performed. Before changing the interrupt skipping count, be sure to clear the T3AEN
and T4VEN bits to 0 to clear the skipping counter (TICNT).
Table 12.38 Setting of Interrupt Skipping Count by Bits 3ACOR2 to 3ACOR0
Bit 6
3ACOR2
0
0
0
0
1
1
1
1
Bit 5
3ACOR1
0
0
1
1
0
0
1
1
Bit 4
3ACOR0
0
1
0
1
0
1
0
1
Description
Does not skip TGIA_3 interrupts.
Sets the TGIA_3 interrupt skipping count to 1.
Sets the TGIA_3 interrupt skipping count to 2.
Sets the TGIA_3 interrupt skipping count to 3.
Sets the TGIA_3 interrupt skipping count to 4.
Sets the TGIA_3 interrupt skipping count to 5.
Sets the TGIA_3 interrupt skipping count to 6.
Sets the TGIA_3 interrupt skipping count to 7.
Table 12.39 Setting of Interrupt Skipping Count by Bits 4VCOR2 to 4VCOR0
Bit 2
4VCOR2
0
0
0
0
1
1
1
1
Bit 1
4VCOR1
0
0
1
1
0
0
1
1
Bit 0
4VCOR0
0
1
0
1
0
1
0
1
Description
Does not skip TCIV_4 interrupts.
Sets the TCIV_4 interrupt skipping count to 1.
Sets the TCIV_4 interrupt skipping count to 2.
Sets the TCIV_4 interrupt skipping count to 3.
Sets the TCIV_4 interrupt skipping count to 4.
Sets the TCIV_4 interrupt skipping count to 5.
Sets the TCIV_4 interrupt skipping count to 6.
Sets the TCIV_4 interrupt skipping count to 7.
Rev. 1.00 Mar. 25, 2008 Page 524 of 1868
REJ09B0372-0100