SH7205 Datasheet, PDF (1129/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.3.14 4-Symbol ECC Processing Result Register n (FL4ECCRESn) (n = 1 to 4)
FL4ECCRESn is a 32-bit read-only register that stores the error correction pattern for the nth error
generated by the 4-symbol ECC circuits and the address for the nth error. The contents of this
register become valid when bits 23 (4EECEN) and 22 (4ECCCORRECT) are set to 1 and a
correction pattern has been generated by the setting of the 4-symbol ECC control register
(FL4ECCCR).
Bit: 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
-
-
-
-
-
LOCn[9:0]
Initial value: 0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
-
-
-
-
-
-
PATn[9:0]
Initial value: 0
0
0
0
0
0
1
1
1
1
1
1
1
1
1
1
R/W: R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
R
Initial
Bit
Bit Name Value
31 to 26 —
All 0
25 to 16 LOCn[9:0] All 1
15 to 10 —
All 0
R/W
R
R
R
Description
Reserved
These bits are always read as 0. The write value should
always be 0.
nth Error Address Indication
Indicates the address of the nth error of the four errors.
Since one sector is handled as 528 bytes, the valid
address range is from H'000 to H'20F. Addresses beyond
the range from H'000 to H'20F are invalid (and indicate
that generation of an error pattern was not possible or
that there were no errors).
The initial value is H'3FF.
The values of these bits that are set after the 4ECCEND
bit in the 4-symbol ECC control register is set to 1 are
valid. Note that starting to read out the data for the next
sector before reading these bits will destroy the data.
Reserved
These bits are always read as 0. The write value should
always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1097 of 1868
REJ09B0372-0100