SH7205 Datasheet, PDF (930/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 19 Serial Sound Interface with FIFO (SSIF)
Initial
Bit
Bit Name Value
R/W Description
0
IDST
1
R Idle Mode Status Flag
This status flag indicates that the serial bus activity has
stopped.
This bit is cleared if EN = 1 and the serial bus are
currently active.
This bit is automatically set to 1 under the following
conditions.
• SSIF = Master transmitter (SWSD = 1 and
TRMD = 1)
This bit is set to 1 if all the data in the system word
to be transmitted has been written to SSITDR and if
the EN bit is cleared to end the system word
currently being output.
• SSIF = Master receiver (SWSD = 1 and TRMD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
• SSIF = Slave transmitter/receiver (SWSD = 0)
This bit is set to 1 if the EN bit is cleared and the
current system word is completed.
Note: If the external master stops the serial bus clock
before the current system word is completed,
this bit is not set.
Note: * The bit can be read or written to. Writing 0 initializes the bit, but writing 1 is ignored.
Rev. 1.00 Mar. 25, 2008 Page 898 of 1868
REJ09B0372-0100