SH7205 Datasheet, PDF (67/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 1 Overview
Classification Symbol
I/O
Operating mode ASEMD
I
control
System control RES
I
MRES
I
WDTOVF
O
Interrupts
NMI
I
IRQ7 to IRQ0 I
PINT7 to PINT0 I
User break
UBCTRG
O
controller (UBC)
Address bus A25 to A0
O
Data bus
D31 to D0
I/O
Name
Function
ASE mode
During RES pin assertion period,
input a low level to operate this LSI
in ASE mode. To operate it in
product chip mode, apply a high
level to this pin.
Enables the E10A-USB emulator
functions in ASE mode.
Fix a high level mode when not using
emulator functions.
Power-on reset This LSI enters the power-on reset
state when this signal goes low.
Manual reset
This LSI enters the manual reset
state when this signal goes low.
Watchdog timer Outputs an overflow signal from the
overflow
WDT.
Non-maskable Non-maskable interrupt request pin.
interrupt
Fix it high when not in use.
Interrupt requests Maskable interrupt request pins.
7 to 0
Level-input or edge-input detection
can be selected. When the edge-
input detection is selected, the rising
edge, falling edge, or both edges can
also be selected.
Interrupt requests Maskable interrupt request pins.
7 to 0
Only level-input detection can be
selected.
User break
trigger output
Trigger output pin for UBC condition
match.
Address bus
Outputs addresses.
Data bus
Bidirectional data bus.
Rev. 1.00 Mar. 25, 2008 Page 35 of 1868
REJ09B0372-0100