SH7205 Datasheet, PDF (1586/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
Bit: 7
6
5
4
3
2
1
0
-
-
-
- RAME3 RAME2 RAME1 RAME0
Initial value: 1
1
1
1
1
1
1
1
R/W: R
R
R
R R/W R/W R/W R/W
Initial
Bit Bit Name Value R/W Description
7 to 4 
All 1 R
Reserved
These bits are always read as 1. The write value should
always be 1.
3
RAME3 1
R/W RAM Enable 3 (page 3 of high-speed on-chip RAM0*)
0: Access to page 3 is disabled.
1: Access to page 3 is enabled.
2
RAME2 1
R/W RAM Enable 2 (page 2 of high-speed on-chip RAM0*)
0: Access to page 2 is disabled.
1: Access to page 2 is enabled.
1
RAME1 1
R/W RAM Enable 1 (page 1 of high-speed on-chip RAM0*)
0: Access to page 1 is disabled.
1: Access to page 1 is enabled.
0
RAME0 1
R/W RAM Enable 0 (page 0 of high-speed on-chip RAM0*)
0: Access to page 0 is disabled.
1: Access to page 0 is enabled.
Note: * For the addresses of each page, see section 29, On-Chip RAM.
30.2.9 System Control Register 2 (SYSCR2)
SYSCR2 is an 8-bit readable/writable register that enables or disables writing from CPU0 to each
page of the high-speed on-chip RAM0.
Setting the RAMWEn (n = 0 to 3) bit in SYSCR2 to 1 enables writing to page n. When the
RAMWEn bit is cleared to 0, writing to page n is ignored. The initial value of the RAMWEn bit is
1.
When clearing the RAMWEn bit to 0, be sure to execute an instruction to read from and write to
the same arbitrary address in page n before setting the RAMWEn bit. If not executed, the data last
written to page n may not be written to the high-speed on-chip RAM.
Rev. 1.00 Mar. 25, 2008 Page 1554 of 1868
REJ09B0372-0100