SH7205 Datasheet, PDF (1430/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
(7) Timing for Composition of Moving Pictures and Graphics by the Output Block
(1) VICLK = 27 MHz synchronous system
VIHSYNC
HS_ext
VICLKENB
720 × 74ns = 53.3us
Moving picture
data
720 pixels
720 pixels
720 pixels
Moving picture data
(After resizing)
480 pixels (moving picture)
480 pixels (moving picture)
480 pixels (moving picture)
Enable signal
for moving picture
Writing resized data
to the data buffer
480 pixels (moving picture)
480 pixels (moving picture)
This period varies because
of asynchronous
(within 1 line).
480 pixels (moving picture)
(2) DCLKIN = approx. 8 MHz
synchronous system
(WQVGA)
Number of DCLKIN close to HS_ext
HSYNC_dck (Internal)
WPH bits
Reading moving picture
data from the data buffer
480 × 125ns = 60us
480 pixels (moving picture)
480 pixels (moving picture)
480 pixels (moving picture)
Graphic data
PDPH bits
VLDPH bits
480 pixels (Gr)
480 pixels (Gr)
480 pixels (Gr)
Synthesized
image data
Gr: Abbreviation of graphics
480 pixels
(Gr + moving picture)
480 pixels
(Gr + moving picture)
When moving picture is not input, the timing chart for the VICLK system shown in (1) is not applicable.
Only graphic data is output in synchronization with HSYNC_dck.
480 pixels
(Gr + moving picture)
Figure 26.12 Timing in the Horizontal Direction
(with Moving Pictures Supplied)
Rev. 1.00 Mar. 25, 2008 Page 1398 of 1868
REJ09B0372-0100