SH7205 Datasheet, PDF(34/1904 Page) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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SH7205 Datasheet, PDF (34/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

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Section 1 Overview

Table 1.1 SH7205 Features

Items

CPU

Specification

â¢ Renesas Technology original SuperH architecture

â¢ Compatible with SH-1, SH-2, and SH-2E at object code level

â¢ 32-bit internal data bus

â¢ Support of an abundant register-set

ï£§ Sixteen 32-bit general registers

ï£§ Four 32-bit control registers

ï£§ Four 32-bit system registers

ï£§ Register bank for high-speed response to interrupts

â¢ RISC-type instruction set (upward compatible with SH series)

ï£§ Instruction length: 16-bit fixed-length basic instructions for improved

code efficiency and 32-bit instructions for high performance and

usability

ï£§ Load/store architecture

ï£§ Delayed branch instructions

ï£§ Instruction set based on C language

â¢ Superscalar architecture including an FPU that allows execution of two

instructions in parallel

â¢ Instruction execution time: Up to two instructions/cycle

â¢ Address space: 4 Gbytes

â¢ Internal multiplier

â¢ Five-stage pipeline

â¢ Harvard architecture

Rev. 1.00 Mar. 25, 2008 Page 2 of 1868

REJ09B0372-0100

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