SH7205 Datasheet, PDF (1318/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
Table 24.26 Timing at which BRDY Interrupts are Generated
Register setting
Buffer State
When Packet is Received
BFRE = 0
BFRE = 1
Buffer full (normal packet received) When packet is received Not generated
Zero-length packet received
When packet is received When packet is received
Normal short packet received
When packet is received
When reading of the received
data from the buffer memory
has been completed
Transaction count ended
When packet is received
When reading of the received
data from the buffer memory
has been completed
Note: This function is valid only in the reading direction of reading from the buffer memory. In the
writing direction, the BFRE bit should be fixed at 0.
Rev. 1.00 Mar. 25, 2008 Page 1286 of 1868
REJ09B0372-0100