SH7205 Datasheet, PDF (186/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 6 Exception Handling
4. After jumping to the address fetched from the exception handling vector table, program
execution starts. This jump is not a delayed branch.
The FPU exception flag field (Flag) of FPSCR is always updated regardless of whether or not an
FPU exception handling has been accepted, and remains set until explicitly cleared by the user
through an instruction. The FPU exception source field (Cause) of FPSCR changes each time a
floating-point operation is executed. When the V bit in the FPU exception enable field (Enable) of
FPSCR is set and the QIS bit in FPSCR is also set, FPU exception handling is generated when
qNaN or ±∞ is input to a floating point operation instruction source.
Rev. 1.00 Mar. 25, 2008 Page 154 of 1868
REJ09B0372-0100