SH7205 Datasheet, PDF (1216/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.20 Interrupt Status Register 1 (INTSTS1)
INTSTS1 indicates the statuses of various interrupts.
This register is initialized by a power-on reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
— BCHG — DTCH ATTCH —
—
—
—
EOF
ERR
SIGN SACK
—
—
—
—
Initial value: -
0
-
0
0
-
-
-
-
0
0
0
-
-
-
-
R/W: R R/W*¹ R R/W*¹ R/W*¹ R
R
R
R R/W*¹ R/W*¹ R/W*¹ R
R
R
R
Initial
Bit
Bit Name Value
R/W Description
15

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
14
BCHG
0
R/W*¹ PORT0 USB Bus Change Interrupt Status*³
This bit is set to 1 when a transition in the full-speed
or low-speed signal level occurs on PORT0 (a
change from J-state, K-state, or SE0 to J-state, K-
state, or SE0). When a BCHG interrupt has occurred,
read the LNST bit several times and confirm that the
same value is read consecutively in order to prevent
chattering.
0: BCHG interrupt has not occurred
1: BCHG interrupt has occurred
13

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1184 of 1868
REJ09B0372-0100