SH7205 Datasheet, PDF (244/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 7 Interrupt Controller (INTC)
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc + m1
1 Icyc + m1 + 2(m2) + m3
IRQ
First instruction in interrupt
service routine
First instruction in multiple interrupt
service routines
m1 m2 m3
F D E EMMM
m1 m2
FD
D E EMMM
FD
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Interrupt acceptance Multiple interrupt acceptance
Figure 7.5 Example of Pipeline Operation for Multiple Interrupts
(No Register Banking)
Interrupt acceptance
3 Icyc + m1 + m2
2 Icyc + 3 Bcyc + 1 Pcyc
3 Icyc
m1 m2 m3
IRQ
Instruction (instruction replacing
interrupt exception handling)
First instruction in interrupt
service routine
F D E EMMME
FDE
[Legend]
m1: Vector address read
m2: Saving of SR (stack)
m3: Saving of PC (stack)
Figure 7.6 Example of Pipeline Operation when IRQ Interrupt is Accepted
(Register Banking without Register Bank Overflow)
Rev. 1.00 Mar. 25, 2008 Page 212 of 1868
REJ09B0372-0100