SH7205 Datasheet, PDF (1374/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
Initial
Bit
Bit name Value
R/W Description
14
INT_VSYC 0
R
VSYNC Input for the Output Block
This bit indicates the state of VSYNC input.
0: VSYNC input signal is not being supplied
1: VSYNC input signal is being supplied. (This bit is
only effective when display is enabled by
GR_MISPLY.)
[Clearing condition]
• Writing 1 to the DIS_VSYC bit of register
GR_INTDIS.
[Setting condition]
• The VSYNC input is supplied.
13
INT_UDFL 0
R
Output Underflow for the Output Block
This bit indicates underflow of the output from the
output block.
0: Output from the output block is normal.
1: Output from the output block underflowed.
[Clearing condition]
• Writing 1 to the DIS_UDFL bit of register
GR_INTDIS.
[Setting condition]
• Underflow of output from the output block.
12
INT_FILD 0
R
Last Line Captured by Output Block
This bit indicates that the output block has finished
capturing the last line in the SE buffer.
0: Last line is not in the output buffer E.
1: Last line has captured in output buffer E.
[Clearing condition]
• Writing 1 to the DIS_FILD bit of register
GR_INTDIS.
[Setting condition]
• Last line being captured in input buffer E for the
output block.
Rev. 1.00 Mar. 25, 2008 Page 1342 of 1868
REJ09B0372-0100