SH7205 Datasheet, PDF (1618/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 31 User Debugging Interface (H-UDI)
Table 31.3 Supported Commands for Boundary Scan TAP Controller
Bits 3 to 0
TI3
TI2
TI1
TI0
0
0
0
0
0
0
0
1
0
0
1
1
0
1
0
0
0
1
1
0
0
1
1
1
Other than the above
Description
EXTEST
SAMPLE/PRELOAD
Emulation TAP controller switching command
IDCODE (initial value)
CLAMP
HIGHZ
Reserved
31.3.3 Boundary Scan Register (SDBSR)
SDBSR is a shift register located on the PAD to control input/output pins of this LSI. This register
cannot be accessed by the CPU. The initial value is undefined.
The EXTEST, SAMPLE/PRELOAD, CLAMP, and HIGHZ commands can be used to perform the
boundary scan test that conforms to the JTAG standard. Table 31.4 shows the correspondence
between the LSI pins and the bits of the boundary scan register.
Rev. 1.00 Mar. 25, 2008 Page 1586 of 1868
REJ09B0372-0100