SH7205 Datasheet, PDF (1836/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 33 Electrical Characteristics
Item
Symbol Min.
Max. Unit Figure
Read data setup time
tNRDS
24

ns Figures 33.51,
33.53
Read data hold time
tNRDH
5

ns Figures 33.51,
33.53
Data write setup time
tNDWS
32 × tpcyc

ns Figure 33.52
Command to status read transition
time
tNCDSR
4 × tfcyc

ns Figure 33.53
Command output off to status read tNCDFSR 3.5 × tfcyc

ns
transition time
Status read setup time
tNSTS
2.5 × tfcyc

ns
Note:
t_fcyc indicates the period of one cycle of the FLCTL clock.
t_wfcyc indicates the period of one cycle of the FLCTL clock when the NANDWF bit is cleared to
0, and indicates the period of two cycles of the FLCTL clock when the NANDWF bit is set to
1.
t
pcyc
indicates
the
period
of
one
cycle
of
the
peripheral
clock
(Pφ).
FCE
(Low)
FCDE
FOE
FWE
FSC
(High)
NAF7 to NAF0
(High)
FRB
t_NCDS
t_NWP
t_NCDH
t_NCDAD1
t_NDOS t_NDOH
Command
Figure 33.49 NAND Type Flash Memory Command Issuance Timing
Rev. 1.00 Mar. 25, 2008 Page 1804 of 1868
REJ09B0372-0100