SH7205 Datasheet, PDF (576/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
Table 12.43 show the TICCR setting and input capture input pins.
Table 12.43 TICCR Setting and Input Capture Input Pins
Target Input Capture
Input capture from TCNT_1 to
TGRA_1
Input capture from TCNT_1 to
TGRB_1
Input capture from TCNT_2 to
TGRA_2
Input capture from TCNT_2 to
TGRB_2
TICCR Setting
I2AE bit = 0 (initial value)
I2AE bit = 1
I2BE bit = 0 (initial value)
I2BE bit = 1
I1AE bit = 0 (initial value)
I1AE bit = 1
I1BE bit = 0 (initial value)
I1BE bit = 1
Input Capture Input Pins
TIOC1A
TIOC1A, TIOC2A
TIOC1B
TIOC1B, TIOC2B
TIOC2A
TIOC2A, TIOC1A
TIOC2B
TIOC2B, TIOC1B
(1) Example of Cascaded Operation Setting Procedure
Figure 12.20 shows an example of the setting procedure for cascaded operation.
Cascaded operation
Set cascading
[1]
Start count
[2]
[1] Set bits TPSC2 to TPSC0 in the channel 1
TCR to B'1111 to select TCNT_2 overflow/
underflow counting.
[2] Set the CST bit in TSTR for the upper and
lower channel to 1 to start the count
operation.
<Cascaded operation>
Figure 12.20 Cascaded Operation Setting Procedure
(2) Cascaded Operation Example (a)
Figure 12.21 illustrates the operation when TCNT_2 overflow/underflow counting has been set for
TCNT_1 and phase counting mode has been designated for channel 2.
TCNT_1 is incremented by TCNT_2 overflow and decremented by TCNT_2 underflow.
Rev. 1.00 Mar. 25, 2008 Page 544 of 1868
REJ09B0372-0100