SH7205 Datasheet, PDF (1279/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 24 USB 2.0 Host/Function Module (USB)
24.3.41 PIPEn Control Registers (PIPEnCTR) (n = 6 to 9)
The PIPEnCTR registers for PIPE6 to PIPE9 are used to confirm the buffer memory status,
change and confirm the data PID sequence bit, determine whether auto buffer clear mode is set,
and set a response PID for the corresponding pipe. These registers can be set regardless of the pipe
selection in PIPESEL.
This register is initialized by a power-on reset. PID[1:0] are initialized by a USB bus reset.
Bit: 15 14 13 12 11 10 9
8
7
6
5
4
3
2
1
0
BSTS — CSCLR CSSTS —
— ACLRM SQCLR SQSET SQMON PBUSY —
—
—
PID[1:0]
Initial value: 0
-
0
0
-
-
0
0
0
0
0
-
-
-
0
0
R/W: R
R R/W*² R
R
R R/W R*¹/ R*¹/ R
R
R
R
R R/W R/W
W*² W*²
Initial
Bit
Bit Name Value
R/W Description
15
BSTS
0
R
Buffer Status
Indicates whether the FIFO buffer assigned to the
corresponding pipe is accessible from the CPU.
The meaning of this bit depends on the settings of
the DIR, BFRE, and DCLRM bits as shown in table
24.13.
0: Buffer not accessible
1: Buffer accessible
14

Undefined R
Reserved
Undefined value is read from this bit. The write value
should always be 0.
Rev. 1.00 Mar. 25, 2008 Page 1247 of 1868
REJ09B0372-0100