SH7205 Datasheet, PDF (376/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
• Single Write Timing Setting Examples
Figures 10.38 to 10.40 show the correspondence between the timing of single write operations and
the set values of the SDRAMm timing register (SDmTR). Table 10.14 lists the SDRAMm timing
register (SDmTR) set values for each figure.
Table 10.14 SDITR Set Value Correspondence Table (Single Write Timing)
Figure
Figure 10.38
Figure 10.39
Figure 10.40
DRAS
010
000
000
DRCD
00
01
01
DPCG
001
001
001
DWR
0
0
1
Single write
CKIO
SDRAM command
ACT WR DSL PRA DSL
Data bus
d
DRCD
DWR
(ACT-WR) (WR-PRA)
DPCG
(PRA-next)
DRAS
(ACT-PRA)
ACT: Row and bank activation command
WR: Write command
DSL: Deselect command
PRA: Precharge-all-banks command
Note: If the interval set in DRAS is longer than the period from when the WR command is issued
until the DWR interval elapses, the DRAS setting is used.
Figure 10.38 Single Write Timing Example 1
Rev. 1.00 Mar. 25, 2008 Page 344 of 1868
REJ09B0372-0100