SH7205 Datasheet, PDF (109/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 2 CPU
Instruction
EXTU.B Rm,Rn
EXTU.W Rm,Rn
MAC.L @Rm+,@Rn+
MAC.W @Rm+,@Rn+
MUL.L Rm,Rn
MULR R0,Rn
MULS.W Rm,Rn
MULU.W Rm,Rn
NEG
NEGC
SUB
SUBC
SUBV
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Rm,Rn
Instruction Code
0110nnnnmmmm1100
0110nnnnmmmm1101
0000nnnnmmmm1111
0100nnnnmmmm1111
0000nnnnmmmm0111
0100nnnn10000000
0010nnnnmmmm1111
0010nnnnmmmm1110
0110nnnnmmmm1011
0110nnnnmmmm1010
0011nnnnmmmm1000
0011nnnnmmmm1010
0011nnnnmmmm1011
Operation
Execu-
tion
Cycles
T Bit
Compatibility
SH2,
SH2E SH4 SH-2A
Byte in Rm is
zero-extended → Rn
1

Yes Yes Yes
Word in Rm is
zero-extended → Rn
1

Yes Yes Yes
Signed operation of (Rn) × 4
(Rm) + MAC → MAC
32 × 32 + 64 → 64 bits

Yes Yes Yes
Signed operation of (Rn) × 3
(Rm) + MAC → MAC
16 × 16 + 64 → 64 bits

Yes Yes Yes
Rn × Rm → MACL
32 × 32 → 32 bits
2

Yes Yes Yes
R0 × Rn → Rn
2
Yes
32 × 32 → 32 bits
Signed operation of Rn × Rm 1
→ MACL
16 × 16 → 32 bits

Yes Yes Yes
Unsigned operation of Rn × 1
Rm → MACL
16 × 16 → 32 bits

Yes Yes Yes
0-Rm → Rn
1

Yes Yes Yes
0-Rm-T → Rn, borrow → T 1
Borrow Yes Yes Yes
Rn-Rm → Rn
1

Yes Yes Yes
Rn-Rm-T → Rn, borrow → T 1
Borrow Yes Yes Yes
Rn-Rm → Rn, underflow → T 1
Over- Yes Yes Yes
flow
Rev. 1.00 Mar. 25, 2008 Page 77 of 1868
REJ09B0372-0100