SH7205 Datasheet, PDF (797/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 16 Serial Communication Interface with FIFO (SCIF)
Initial
Bit
Bit Name Value R/W Description
5, 4
TTRG[1:0] 00
R/W Transmit FIFO Data Trigger
Set the quantity of remaining transmit data which sets
the transmit FIFO data register empty (TDFE) flag in the
serial status register (SCFSR). The TDFE flag is set to 1
when the quantity of transmit data in the transmit FIFO
data register (SCFTDR) becomes less than the set
trigger number shown below.
00: 8 (8)*
01: 4 (12)*
10: 2 (14)*
11: 0 (16)*
Note: * Regardless of the input value, CTS level and
RTS level have no effect on the transmit
operation and the receive operation,
respectively.
3
MCE
0
R/W Modem Control Enable
Enables modem control signals CTS and RTS.
For channels 1 to 5 in clock synchronous mode, MCE bit
should always be 0.
0: Modem signal disabled*
1: Modem signal enabled
Note: * CTS is fixed at active 0 regardless of the
input value, and RTS is also fixed at 0.
2
TFRST
0
R/W Transmit FIFO Data Register Reset
Disables the transmit data in the transmit FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
1
RFRST
0
R/W Receive FIFO Data Register Reset
Disables the receive data in the receive FIFO data
register and resets the data to the empty state.
0: Reset operation disabled*
1: Reset operation enabled
Note: * Reset operation is executed by a power-on
reset.
Rev. 1.00 Mar. 25, 2008 Page 765 of 1868
REJ09B0372-0100