SH7205 Datasheet, PDF (1145/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
(1) Overview of 4-Symbol ECC Circuit
The 4-symbol ECC circuit in the FLCTL is capable of correcting up to10 bits per symbol, which
makes a maximum of 40 bits for four symbols. However, the circuit corrects up to 32 bits because
the data in the flash memory data area is counted as eight bits per symbol.
Error correction pattern generation means generation of information necessary for correcting
errors, not execution of error correction. For details, see (3) 4-Symbol ECC Error Correction
Pattern Generation.
The 4-symbol ECC circuit is roughly divided into three stages (figure 23.17).
1. ECC generator
2. Error count detector
3. Error correction pattern generator
ECC generation and error count detection can be executed continuously while error correction
pattern generation is executed on a sector-by-sector basis.
External memory
512 bytes (data)
+
10 bytes (ECC)
Flash memory
4-symbol ECC
generator
4-symbol ECC
error count
detector
4-symbol ECC
error correction
pattern
generator
4-symbol ECC circuit
FLCTL
Register
Register
ECC error count register
4-symbol ECC processing result 1
4-symbol ECC processing result 2
4-symbol ECC processing result 3
4-symbol ECC processing result 4
Figure 23.17 4-Symbol ECC Circuit
Rev. 1.00 Mar. 25, 2008 Page 1113 of 1868
REJ09B0372-0100