SH7205 Datasheet, PDF (1152/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 23 AND/NAND Flash Memory Controller (FLCTL)
23.6 DMA Transfer Specifications
The FLCTL can request DMA transfers separately to the data area FLDTFIFO and control code
area FLECFIFO. Table 23.6 summarizes DMA transfer enable or disable states in each access
mode.
Table 23.6 DMA Transfer Specifications
FLDTFIFO
FLECFIFO
Sector Access Mode
DMA transfer enabled
DMA transfer enabled
Command Access Mode
DMA transfer enabled
DMA transfer disabled
For details on DMAC settings, see section 11, Direct Memory Access Controller (DMAC).
Rev. 1.00 Mar. 25, 2008 Page 1120 of 1868
REJ09B0372-0100