SH7205 Datasheet, PDF (1360/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 26 2D Graphics Engine (2DG)
• Final picture resolution: WQVGA (480 x 234) or QVGA (320 x 240)
• Capacity of input/output buffers for graphics (each is in a double-buffer configuration)
 Input buffer E for the output block: 16bits x 512 words x 2 planes
 Input buffers A and B for the blitter: 16 bits x 64 words x 2 planes, each
 Output buffer C for the blitter: 16 bits x 256 words x 2 planes
Figure 26.1 is a block diagram of the 2DG.
Peripheral bus
CPU
interface
Registers
Buffer SA
SA2
SA1
16 bits x
64 words
I/O buffer control
Buffer SB
SB2
SB1
16 bits x
64 words
Buffer DC
DC2
DC1
16 bits x
256 words
2DG
Graphic processor
Resizing block
Blitter
BufferSE
SE2
SE1
16 bits x
512 words
Output
block
Blending
processor
Data
buffer
Output
controller
VIHSYNC
VIVSYNC
VICLK
VIDATA[7:0]
VICLKENB
Video In
DAC
RGB output CSYNC DCLKIN
CBU REXT
Panel unit
Clock
[Legend]
Buffer SA:
Buffer SB:
Buffer DC:
Buffer SE:
Input source buffer A on blitter
Input source buffer B on blitter
Output destination buffer C on blitter
Input source buffer E on output block
Note: Each of the buffers SA, SB, DC and SE has a double-buffer structure.
The abbreviations are SA1 and SA2, SB1 and SB2, DC1 and DC2, and SE1 and SE2, respectively.
Figure 26.1 Block Diagram of the 2DG
Rev. 1.00 Mar. 25, 2008 Page 1328 of 1868
REJ09B0372-0100