SH7205 Datasheet, PDF (189/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Exception Type
Trap instruction
Slot illegal instruction
General illegal instruction
Integer division exception
Section 6 Exception Handling
Stack Status
SP
Address of instruction
after TRAPA instruction
SR
32 bits
32 bits
SP
Jump destination address
of delayed branch instruction
32 bits
SR
32 bits
SP
Start address of general
illegal instruction
SR
32 bits
32 bits
SP
Start address of relevant
integer division instruction
SR
32 bits
32 bits
Rev. 1.00 Mar. 25, 2008 Page 157 of 1868
REJ09B0372-0100