SH7205 Datasheet, PDF (1578/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 30 Power-Down Modes
Initial
Bit Bit Name Value R/W Description
2
MSTP22 0
R/W Module Stop 22
When set to 1, the clock supply to UBC0 is halted.
0: UBC0 runs.
1: Clock supply to UBC0 is halted.
1
MSTP21 0
R/W Module Stop 21
When set to 1, the clock supply to UBC1 is halted.
0: UBC1 runs.
1: Clock supply to UBC1 is halted.
0

0
R
Reserved
This bit is always read as 0. The write value should always
be 0.
30.2.3 Standby Control Register 3 (STBCR3)
STBCR3 is an 8-bit readable/writable register that controls the operation of modules in power-
down modes.
Note: When writing to this register, see section 30.4, Usage Notes.
Bit: 7
6
5
4
MSTP
37
-
MSTP
35
-
Initial value: 1
1
1
1
R/W: R/W R R/W R
3
2
1
0
-
MSTP MSTP MSTP
32
31
30
1
1
1
0
R R/W R/W R/W
Initial
Bit Bit Name Value R/W Description
7
MSTP37 1
R/W Module Stop 37
When set to 1, the clock supply to the ATAPI is halted.
0: ATAPI runs.
1: Clock supply to ATAPI is halted.
6

1
R
Reserved
This bit is always read as 1. The write value should always
be 1.
Rev. 1.00 Mar. 25, 2008 Page 1546 of 1868
REJ09B0372-0100