SH7205 Datasheet, PDF (429/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 11 Direct Memory Access Controller (DMAC)
Initial
Bit
Bit Name Value R/W Description
5 to 0 DCTG[5:0] 000000 R/W (Continued)
101100: SSU_1 reception
101101: SSU_1 transmission
101110: A/D converter
101111: 2DG output
110000: 2DG BLT input A
110001: 2DG BLT input B
110010: 2DG BLT output C
110011: FLCTL_0 transmission/reception
110100: FLCTL_1 transmission/reception
110111: RM0_0 (RCAN)
111000: RM0_1 (RCAN)
Other than the above: Setting prohibited
Note:
Modify the settings of bits of this register other than the reload function enable bits (BRLOD,
SRLOD, and DRLOD) only when the corresponding channel is not undergoing single
operand transfer (the DASTS bit of the DMA arbitration status register (DMASTS) is 0) and
DMA transfer is disabled (the DMST bit of the DMA activation control register (DMSCNT) is
0 or the DEN bit of DMA control register B (DMCNTBn) is 0). In other cases, operation is not
guaranteed when data is written to this register.
Rev. 1.00 Mar. 25, 2008 Page 397 of 1868
REJ09B0372-0100