SH7205 Datasheet, PDF (661/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 12 Multi-Function Timer Pulse Unit 2 (MTU2)
12.7.9 Contention between TGR Read and Input Capture
If an input capture signal is generated in the T1 state of a TGR read cycle, the data that is read will
be the data in the buffer before input capture transfer.
Figure 12.104 shows the timing in this case.
TGR read cycle
T1 T2
Pφ
Address
TGR address
Read signal
Input capture
signal
TGR
N
M
Internal data
bus
N
Figure 12.104 Contention between TGR Read and Input Capture
Rev. 1.00 Mar. 25, 2008 Page 629 of 1868
REJ09B0372-0100