SH7205 Datasheet, PDF (861/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 17 Synchronous Serial Communication Unit (SSU)
Start
[1]
Initial setting
[2]
Read the TDRE bit in SSSR.
No
TDRE = 1?
Yes
Write transmit data to SSTDR
TDRE automatically cleared
Data transferred from SSTDR to SSTRSR
TDRE set to 1 to start transmission
[3]_No
Read SSSR
RDRF = 1?
Yes
ORER = 1?
No
Read receive data in SSRDR
Yes [4]
RDRF automatically cleared
Consecutive data
transmission/reception?
No
[5]
Yes
[1] Initial setting:
Specify the transmit/receive data format.
[2] Check the SSU state and write transmit data:
Write transmit data to SSTDR after reading and
confirming that the TDRE bit in SSSR is 1. The TDRE
bit is automatically cleared to 0 and transmission/
reception is started by writing data to SSTDR.
[3] Check the SSU state:
Read SSSR confirming that the RDRF bit is 1.
A change of the RDRF bit (from 0 to 1) can be notified
by RXI interrupt.
[4] Receive error processing:
When a receive error occurs, execute the designated
error processing after reading the ORER bit in SSSR.
After that, clear the ORER bit to 0. While the ORER bit is
set to 1, transmission or reception is not resumed.
[5] Procedure for consecutive data transmission/reception:
To continue serial data transmission/reception, confirm
that the TDRE bit is 1 meaning that SSTDR is ready to be
written to. After that, data can be written to SSTDR. The
TDRE bit is automatically cleared to 0 by writing data to
SSTDR.
Read the TEND bit in SSSR
No
TEND = 1?
Yes
Clear the TEND bit in SSSR to 0
Error processing
No
One bit period elapsed?
Yes
Clear bits TE and RE in SSER to 0
End transmission/reception
Note: Hatching boxes represent SSU internal operations.
Figure 17.9 Flowchart Example of Simultaneous Transmission/Reception (SSU Mode)
Rev. 1.00 Mar. 25, 2008 Page 829 of 1868
REJ09B0372-0100