SH7205 Datasheet, PDF (359/1904 Pages) Renesas Technology Corp – Renesas 32-Bit RISC Microcomputer SuperHTM RISC engine Family / SH7200 Series

Section 10 Bus State Controller (BSC)
CKIO
Multiple writes
SDRAM command
ACT WR WR WR PRA ACT WR PRA
Data bus
d0
d1
d2
d3
Row address A
ACT: Row and bank activation command
WR: Write command
PRA: Precharge-all-banks command
Row address B
Figure 10.19 Multiple Write Timing Example
(Multiple Writes of 4 Data Units, Shortest Timing Settings)
Access Spanning Rows
(b) Single Read/Single Write Access
Figure 10.20 shows a timing example for single read operation and figure 10.21 for single write
operation. The access timing is modified by means of settings in the SDRAMm timing register
(SDmTR).
CKIO
Single read
SDRAM command
ACT RD PRA
Data bus
d0
ACT: Row and bank activation command
RD: Read command
PRA: Precharge-all-banks command
Figure 10.20 Single Read Timing Example (Shortest Timing Settings)
Rev. 1.00 Mar. 25, 2008 Page 327 of 1868
REJ09B0372-0100